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The fastest path to analog reuse is through direct layout migration

Tue, 24 Mar 2026 19:26:24 GMT

Preserving layout, not rebuilding, is the key to scalable analog migration

When migrating analog layout between foundries or process nodes, the work is often perceived as complex. Analog circuits can be described as overly sensitive, fragile, or difficult to transfer reliably, but that view misses the key insight: well-designed analog circuits are inherently robust, and direct layout migration leverages that robustness effectively.

By preserving the layout, engineers can make device sizing decisions based on accurate extracted parasitic data rather than schematic estimates, as post-layout simulation with extracted parasitics remains the ultimate safety net. Any physical differences introduced during migration—whether due to rule-driven adjustments, layer mapping, or minor device reconstruction—are captured in simulation, ensuring the migrated layout meets electrical specifications before tapeout. The main challenges in migration are therefore not due to circuit fragility, but rather to reconciling the new process constraints while maintaining symmetry, placement, routing, and hierarchy. For analog layouts, retaining the original geometry and hierarchy is more valuable than rebuilding devices from parameters, because the original layout embodies silicon-validated tuning and design decisions.

In essence, direct layout migration allows designers to carry forward proven design decisions, physical tuning, and layout expertise, while post-layout simulation ensures correctness in the new process. Tuning the circuit by adjusting component sizes can be applied directly to the layout and specifications met through accurate simulations with physical data. By preserving the layout hierarchy and the implementation that already works, this approach avoids the time, effort, and uncertainty of schematic-driven redesign. Rapid and direct layout migration takes engineers to simulation of a real circuit and tape-out.

In an era of multi-foundry strategies and continuous node evolution, direct layout migration is not just efficient, it's a clear competitive advantage.

Why Layout Migration Beats Schematic Migration for Analog IP

Thu, 08 Jan 2026 23:22:15 GMT

For analog IP reuse, the layout is the source of truth

 Ask any analog designer how they want to migrate IP, and the answer is almost always the same: don’t rebuild it, move it. Engineers want to migrate the existing layout, preserving silicon-proven physical implementation and minimizing risk. In practice, however, direct layout migration is often dismissed as too difficult or impractical, pushing teams toward schematic updates and full layout regeneration. While schematic-first approaches may appear cleaner on paper, experience consistently shows that direct layout migration delivers lower risk, faster turnaround, and more predictable results, especially for analog and mixed-signal IP.

Scale further amplifies this advantage. Even the most advanced schematic retargeting tools work best on small to medium, well-structured blocks. They do not scale well to large analog IP such as wireless cores or SerDes, which are deeply hierarchical and heavily dependent on layout-defined behavior: parasitics, coupling, symmetry, and routing topology, that is not fully captured in schematics. As complexity grows, automation breaks down and manual rework dominates the schedule.

Schematic migration still plays an important role. It enables early simulation, supports LVS, and provides functional reference. But a flow that relies on schematics to regenerate layout is not true migration.

In practice, successful migrations treat the layout as the real circuit, schematics are only a description . Direct layout migration preserves silicon-proven physical relationships: placement, matching, routing topology, and parasitics, that simply cannot be reconstructed from schematics alone. By building on what already works, teams reduce silicon risk, avoid unnecessary redesign cycles, and dramatically shorten time to reuse in a new process or foundry. Schematic retargeting still has value for well-constrained sub-blocks or localized updates, but for large, mature and complex analog IP, rebuilding from scratch almost always introduces more uncertainty than improvement. Migration without the layout is not modernization—it's just redesign by another name.

The Silent Leak in Semiconductor Security

Fri, 31 Oct 2025 15:12:21 GMT

Why PDKs Are the Next Frontier for IP Theft

The semiconductor industry just got a harsh reminder that even the most advanced fabs aren’t immune to leaks. TSMC, the world’s most valuable chipmaker, recently uncovered a serious internal breach involving its 2nm process technology. Several employees, both current and former, were caught capturing and sharing confidential process-integration images, leading to immediate terminations and arrests under Taiwan’s National Security Act.

Not long before, South Korea's SK Hynix faced a similarly alarming case: an engineer printed 4,000 pages of proprietary process data and smuggled them out in shopping bags before joining Huawei. The simplicity of the method underscores a chilling truth, sometimes the biggest threats don’t come from hackers, but from people inside the building.

When Secrets Become Strategy

These incidents are part of a growing pattern. Semiconductor IP theft is accelerating because the stakes have never been higher. Every process node represents billions of dollars of R&D and national security value. Even partial access to process data, recipes, layout rules, packaging methods, can shave years off a competitor’s development cycle.

But the real danger isn’t always buried deep in the fab. Increasingly, it’s distributed intentionally, through something every foundry must share with customers: the Process Design Kit, or PDK.

PDKs: The Hidden Vulnerability

A PDK is the bridge between the fab and the designer, a package that contains the design rules, transistor models, layout libraries, and parameterized cells (Pcells) needed to build chips that match the foundry’s process. While PDKs don’t reveal the entire manufacturing recipe, they expose just enough of the underlying physics and geometry to make them incredibly valuable. From transistor dimensions to metal stack details, a PDK provides a roadmap of what a foundry’s process can (and can’t) do.

And here’s the problem: most PDKs are not truly secure.

Anyone with a compatible EDA tool can open a PDK, explore its models and layouts, and gain insight into the foundry’s performance limits. Each file describes how devices behave, how they scale, and how far the process can be pushed. In the wrong hands, that’s gold.

Every Copy Is a Risk

Foundries have added layers of verification, licensing, and digital tracking before releasing PDKs, but each external copy is a new point of vulnerability. If a foundry like TSMC can suffer an internal breach, what happens when hundreds of copies of its PDKs circulate among design partners worldwide?

Even if the PDK alone can’t recreate a process, it’s still a valuable piece of the puzzle. Combine it with stolen images, measurements, or partial recipes, and an adversary could map out critical details of an advanced node.

Securing the Design Chain

Protecting semiconductor IP now means protecting the design ecosystem. That includes encrypting PDK contents, watermarking files, restricting access, and auditing every use. Security can’t stop at the fab door, it has to extend into the EDA tools, the partner companies, and the individual engineers using them.

Because the next big leak in the chip world might not come from a spy with a camera. It might come from a PDK sitting quietly on someone’s laptop.

Explore PDK security with IN2FAB's Secure PDK .

Inspiring the Next Generation of Chip Designers

Thu, 07 Aug 2025 20:15:17 GMT

IN2FAB Talks Semiconductors at UMaine’s Semiconductor Camp

IN2FAB Technology had the opportunity to speak with a group of motivated high school students attending a Semiconductor Camp. The program, hosted by the University of Maine and funded by the National Science Foundation, brought together 22 students from across five states for an in-depth look at microelectronics. The camp was hosted by UMaine's Electrical and Computer Engineering department , supported by a team of graduate students. Other UMaine staff and local high school teachers gave informative talks and worked with the students throughout the week.

The 45-minute presentation was followed by informal conversations along with. As students continued their project work, they asked questions and shared what they had been working on during the week, and their curiosity and thoughtfulness stood out. The questions they raised reflected both an understanding of the field and a desire to connect their learning to practical outcomes.

The semiconductor industry is constantly evolving, driven by advances in technology, increasing design complexity, and a changing global landscape. Future engineers will need to adapt quickly, learn continuously, and approach new challenges with creativity and collaboration. Equally important is the fresh thinking and energy that younger generations bring to the field, forming bold ideas and asking hard questions.

In addition to classroom time, students were given a tour of a local Texas Instruments manufacturing site to see cleanrooms and production facilties for themselves. This rare behind the scenes tour showed the complexity and precision of semiconductor manufacturing including the various stages of photolithography, wafer processing and testing.

They also gained insight into the scale and sophistication of the equipment used, the importance of automation and robotics,seeing how physics, chemistry, and engineering principles come together in a real-world setting. Experienceing the high-tech environment and the collaboration between skilled engineers and technicians can help students connect classroom learning to actual careers in science and technology.

Securing photonics investments

Wed, 02 Apr 2025 21:59:36 GMT

Photonics and the Tech Race: Safeguarding National and Corporate Security in the Battle for Dominance

In the early 2000s, semiconductor and system firms attracted substantial venture capital, with nearly $3.7 billion invested in 2000 alone. However, by 2010, VC investments in electronics, including semiconductors, had declined to 6%, and by 2022, this figure dropped to under 1%.

Now VCs have returned to the semiconductor sector with a positive outlook and increasing investments. In particular, new and emerging photonics startups have attracted significant funding due to their potential to revolutionize high-demand computing environments. In October 2024, Lightmatter raised $400 million in a venture capital deal that valued the company at $4.4 billion. Similarly, Xscape Photonics closed a $44 million Series A funding round and Celestial AI secured an additional $250 million in VC to develop photonics in AI chip connectivity. Happy days have returned for chip startups.

New security technology means the steps required to protect a PDK are neither complex nor difficult. Existing parameterized cell (Pcell) code can be updated with license calls, while graphical databases can be converted to secure versions in minutes. The updated files are then automatically linked to security functions that check whether the user has a valid license to open and use the PDK. All of these license and security functions are handled by IN2FAB's Secure PDK software which forms a bridge between the design environment and industry standard licensing products, delivering file security with minimal time and effort.

In addition to safeguarding foundry information, securing the PDK protects circuits that are built using them. Design databases are useless without details of the components inside, and secure PDK locks this data away to protect foundries and fabless companies alike. With such enormous sums being invested in photonics, investors are taking a huge risk in leaving files that contain the products wide open to compromise, copying and outright theft.

In the rapidly evolving field of photonics, protecting sensitive data is more critical than ever. Ensuring robust safeguards around intellectual property, maintains data integrity, and prevents losses of critical research and innovation. By implementing core database security, organizations can fortify their products against cyber threats as competing companies and nations battle for technical dominance. As photonics continues to drive advancements across a wide spectrum of technology, prioritizing file security is not just a best practice, it’s a necessity for sustaining progress and leadership in the industry.

Process Design Kits lack vital security

Mon, 13 Jan 2025 17:28:57 GMT

Unsecured PDKs and Pcells are a major security risk

Anyone that has tried to obtain a Process Design Kit (PDK) from a foundry will have a story of how much pain they endured to get it. Where once PDKs could be licensed on the back of a mutual NDA, foundries now demand background checks, audits, and an exhaustive security review. Some users have described the process of obtaining an advanced PDKs taking up to a year, and even access to mature PDKs can take months.

Skill-based PDK software is not compatible with industry standard security and licensing tools, so it's difficult to restrict them using electronic licenses. Commercial license software can't be compiled into PDKs so they can't be controlled in the same way as design tools. Checking licenses via an external utility is possible, but the interface can be vulnerable to hacking and compromise.

The problem of PDK and component security isn't just restricted to foundries, as many fabless companies produce their own PDKs which give them a critical competitive advantage. Industry sectors focused on emerging technologies such as silicon photonics often deliver their most critical IP in the form of PDKs while military, space and other defense related sectors rely on specialized components in PDKs to develop their products.

IN2FAB has built an extensive knowledge of PDKs and databases from the development of its migration tools and services. Internal development has led to Secure PDK, a new product to protect databases from unauthorized use. Secure PDK integrates cybersecurity by adding calls to check licenses in the Pcell code to lock down the functions inside. This renders the Pcells inactive without an electronic license, and prevents the components inside being used or seen.

Unsecured parameterized cells and PDKs are more than just a technical problem—they are a gateway to corporate espionage, economic loss, and national security threats. By addressing these vulnerabilities, Secure PDK can protect innovation, secure critical infrastructure, and maintain the integrity of the semiconductor supply chain.

IN2FAB Joins the Microelectronics Commons

VF1935 — Fri, 25 Oct 2024 16:54:07 GMT

Driving Circuit Migration and PDK Security in the Microelectronics Commons

As the microelectronics industry moves into the next era of innovation, circuit migration and intellectual property (IP) security are becoming key priorities. The U.S. Department of Defense’s Microelectronics Commons initiative provides the ideal environment for companies to tackle these challenges head-on. For companies in the semiconductor space, the ability to securely migrate circuits and protect IP is critical to maintaining competitive advantages and ensuring national security.

IN2FAB's focus on circuit migration and IP security aligns perfectly with the Commons’ goals to address critical vulnerabilities in the semiconductor industry, enabling faster, safer, and more secure deployment of new technologies.

Paving the Way for Domestic Semiconductor Innovation

Circuit migration and PDK security are essential components of the modern semiconductor landscape, enabling companies to transition designs to advanced fabrication technologies while safeguarding their intellectual property. As the demand for innovative, high-performance chips continues to grow, the ability to securely migrate circuits and protect proprietary design information will become increasingly important.

By focusing on innovation to develop and secure the semiconductor supply chain, IN2FAB is helping companies maintain a competitive edge in an industry where IP development and security are paramount.

Migrating and Modifying Standard Cell Libraries

Tue, 19 Mar 2024 22:43:55 GMT

Automated modifications to standard cell libraries saves time and money

Predefined logic functions in standard cells lie at the heart of digital circuit design. These components form the bedrock in digital circuits, where powerful place & route tools use them to build circuits that drive the electronics revolution.

Developing and validating a new standard cell library for a new technology node can be expensive due to the investment required in design, and verification efforts. Companies must weigh the cost of updating the standard cell library against the benefits gained from utilizing the new technology node. Depending on the resources available, updating a standard cell library to a new technology node may require significant time, manpower, and computational resources. Balancing these constraints while meeting project deadlines and quality goals can be a challenge.

In addition to layer and gate size changes, each process node comes with its own set of design rules governing minimum feature sizes, spacing, and other layout constraints. Engineers must also choose optimum cell height and routing pitch to delivery maximum area and routing density. The complexity of these constraints prevents designers from running tests to find the optimum values for the new technology.

The rapid processing times for entire libraries mean that designers can adjust parameters and run tests in a matter of minutes. Cell sizes and routing grids can be adjusted to evaluate their impact across the entire cell library, while detailed information such as DFM rules can be factored in to the process as required.

Efficient standard cell migration combined with grid adjustment and DFM integration allows engineers to evaluate and test new technologies with minimum effort. This ensures companies can protect and leverage their standard cell IP for years to come.

Unlocking Innovation: The Benefits of Outsourcing Semiconductor IP Migration

Wed, 13 Dec 2023 13:40:42 GMT

Rapid porting accelerates SoC development using existing cores or 3rd party IP.

In today's rapidly evolving semiconductor landscape, companies are constantly seeking ways to stay competitive and innovative. Fabless companies rely on platforms of analog and mixed signal IP cores for internal SoC development, while specialist IP companies need to deliver products to meet their customers’ requirements to win license revenue. One strategy gaining popularity is outsourcing IP migration. While some may be hesitant to entrust critical aspects of their business to external partners, the benefits of outsourcing IP migration can be substantial, contributing to enhanced efficiency, cost savings, and accelerated innovation.

Cost Efficiency

Outsourcing IP migration can be a game-changer for businesses looking to optimize their budget. By leveraging the expertise of external teams, companies can significantly reduce operational costs associated with using an in-house development team. This allows organizations to reallocate resources to other strategic areas while still receiving top-notch IP migration services.

Access to Specialized Skills

In the ever-evolving tech landscape, staying ahead often requires specialized skills. Outsourcing provides access to migration specialists with years of experience in schematic and layout migration. Whether it's migration analysis, component mapping, database processing and project management, outsourcing partners can bring a level of specialization that may be challenging to achieve with an in-house team.

Agility and Flexibility

Outsourcing offers unparalleled flexibility, allowing businesses to scale their resources based on project needs. Whether it's scaling up for a major IP project or scaling down during quieter periods, outsourcing provides the agility to adapt to changing requirements. This flexibility enables companies to respond more effectively to market demands and evolving business priorities.

Accelerated Time-to-Market

Ever shortening development cycles mean that time is of the essence. Outsourcing can expedite the development process, leading to faster time-to-market for new foundries or process nodes. External teams, often operating in different time zones, can work around the clock, ensuring that development cycles are completed more efficiently and deadlines are met promptly.

Risk Mitigation and Compliance

Entrusting IP migration to external experts means sharing the associated risks. IP migration specialists are well-versed in managing various types of risks, including schedules and technical challenges. Detailed migration project schedules are clearly defined, and migrated IP is delivered in a new process at a fixed schedule and cost.

Focus on Core Competencies

Outsourcing allows businesses to concentrate on their core competencies and strategic objectives. By delegating non-core functions like IP migration to external specialists, organizations can direct their energy and resources toward activities that drive growth and competitiveness. This strategic alignment can lead to a more streamlined and efficient operation.

Outsourcing IP migration is more than just a cost-saving strategy; it's a catalyst for innovation and efficiency. By tapping into external expertise, businesses can navigate the complexities of IP migration with agility and speed. While challenges may exist, the benefits of outsourcing are proving to be a transformative force for companies seeking to unlock new opportunities and stay at the forefront of their industries.

OSIRIS DFM for Standard Cells

Wed, 16 Aug 2023 20:41:03 GMT

IN2FAB to add DFM capability to OSIRIS tools with support from Innovate UK

IN2FAB Technology is enhancing its schematic and layout migration products to deliver interactive DFM implementation for standard cell libraries and digital design. The new program will deliver an efficient design environment that allows engineers to evaluate enhanced rule sets against their circuits across libraries containing hundreds of individual elements. Single rule grouped rule changes can be run at the touch of a button, while checking configurations will be automatically generated.

The OSIRIS DFM tool will represent an important new product in IN2FAB's portfolio. The company's primary focus has been on tools and services for translating silicon IP from one manufacturing process to another. OSIRIS DFM delivers an efficient new interface to explore yield enhancement options and improve circuit performance .

Semiconductors must observe physical rules which define the elements in a circuit, and these can be extremely complex. Extra constraints called Design for Manufacturing (DFM) rules can be applied to improve performance and manufacturing yield, but these can affect chip size, complexity and cost.

Semiconductor manufacturing is rapidly increasing in complexity and silicon density, placing greater challenges to engineers and design software manufacturers. IN2FAB's new software will help designers keep pace with these changes and choose the best options for the next generation of silicon.

Translating External Schematic Databases to Cadence Virtuoso

Sun, 25 Jun 2023 20:37:32 GMT

Database translation tools enable rapid circuit integration

Schematic databases lie at the heart of electronics design. Systems are conceived and constructed using schematic editing tools that build the circuits for the most complex products.

EDA tools like Cadence Virtuoso provide designers with a comprehensive platform for IC development, but some design teams use other tools in parallel or as their main design platform. While these can deliver high levels of functionality, integrating circuits from these tools with industry standards like Cadence presents a challenge for semiconductor companies.

Translating external schematic databases is a complex task due to the differences in file formats and data structures. Without a streamlined process for integration, designers may need to recreate or manually re-enter circuits, resulting in time-consuming and error prone efforts.

Direct translation tools for new formats are constantly being developed, and conversion programs are currently available for:

Viewlogic/Viewdraw
LTSpice
Xschem
SLED/Smash

Seamlessly integrating external schematic databases into Cadence Virtuoso brings significant advantages to IC design teams. Designers can leverage pre-design circuits and IP from third party vendors and take advantage of Virtuoso’s advanced design features. Companies can also integrate databases that result from company purchases and mergers, allowing newly acquired design teams to move their products in to a single design platform.

IN2FAB’s database translation and migration tools provide a rapid and efficient way to move circuits from third party tools to Cadence Virtuoso. Delivering a path to integrate designs which saves time and money while achieving optimal circuit performance.

Standard Cell Library Reuse

Wed, 19 Apr 2023 22:47:35 GMT

Migrating standard cells pays huge dividends

Even though commercial libraries are available, many companies develop their own to gain a technical advantage or simply avoid paying license fees. These become the bedrock of the design process and are used across a wide variety of circuits. However, this presents a problem when a company moves to a new technology as the library must be ported before any new products can be developed. This places a strain on the company’s library group who must make the standard cells available in the shortest possible time, which can lead to compromises in the cell design.

Software or Service?

Wed, 19 Apr 2023 22:47:33 GMT

Should a migration project be performed internally or through a design service?

Another advantage of structuring the work in this way is that it allows design engineers to pick out the most critical parts of a circuit and move them to the top of the queue. Migrated schematics of the critical elements are soon followed by layout in the new process, enabling a full simulation in the target process, complete with extracted parasitic data. Simply simulating a schematic and adjusting component sizes offers little advantage when it comes to migration as it relies on a complete re-layout which is usually the bottleneck when delivering analog IP.