OSIRIS layout migration tools are designed to simplify the complexities of translating circuit elements between processes and foundries. Interactive tools identify the elements in each circuit and guide the user through the process of translating them between the original and new design kits.
Shape based data is adjusted and translated to new layers while advanced circuit elements such as parameterized cells and other complex circuit elements are translated and placed in to the new circuit. This places components straight from the new design kits ensures compatilbility with the new design environment and verification tools.
Design migration takes place interactively within the layout editor, giving engineers the freedom to adjust or modify their design at any time. Control and processing options also allows sections of the design hierarchy to be translated, giving users complete control over the migration process.
OSIRIS migrates all circuit elements and places equivalent objects in the new database. Parameterized cells are mapped to an equivalent device type from the new design kit and properties are translated and adjusted while component placements adjusted to the optimal positions. All other circuit elements such as shapes, vias and guard rings are translated to new layers and adjusted to match the requirements of the new process rules.
Interactive and intuitive user interfaces search the original circuit to identify core components and help guide the user to translate them to the new design requirements. Physical properties can be mapped directly or given further processing to resolve core differences between component construction and generate compatible layout from the source.
OSIRIS layout migration features a host of features and capabilities to resolve the most complex mapping problems and generate layout tha tmatches the original circuit while meeting the new design rules.
OSIRIS generates a fully editable database that contains the same circuit elements as the original. Users can control the data translation and adjust layout using editing tools to further enhance the circuit. The topology, hierarchy and component make up of the migrated circuit match the source data to ensure that it can be further edited without restriction.
Differences between the source and target design rules often mean that component placement and interconnect must be adjusted to maintain aligment and connectivity. Changes in rules such as contact size and gate spacing can mean components become separated from overlapping cells and from routing shapes.
OSIRIS recognises component alignment in the circuits and makes small adjustments to the placement and routing in the migrated circuit to align and reconnect devices. Connections through contact overlap or wire and polygon interconnect are automatically resloved to retain the alignment and matching of critical devices..
OSIRIS features a host of interactive layout adjustment tools that allow users to update the circuit layout and resolve critical rules or layout requirements.
Shapes and layers can be adjusted to meet new DRC rules on single circuits or through the design hierarchy. Interactive circuit changes can also be made using a layout editor to resolve final design rule issues and complete the migration process.