The
GLOBALFOUNDRIES 22FDX®
Silicon on Insulator process
delivers FinFET-like
performance and energy
efficiency at the cost of
28nm planar technology.
22FDX®
technology gives designers
high performance at low
power for 5G, IoT and
ultra-efficient RF and
analog circuits. 22FDX®
is gaining signficant
traction in the industry,
giving IP vendors new
licensing opportunities for
their products.
IN2FAB Technology has joined Global Foundries’ FDXcelerator™ program as a design service and EDA partner to streamline the migration process and help companies move their IP to this new technology in the most efficient way possible. IN2FAB's advanced design migration technology transfers planar circuits to 22FDX® in a fraction of the time and cost taken for a circuit redesign.
Semiconductor manufacturing
processes continue to
advance with ever-decreasing
geometry sizes and extreme
levels of integration.
Recent innovations
have seen foundries move on
from the bulk silicon
devices that had been the
mainstay of semiconductor
engineering to meet the
demands of the nano-meter
technology.
Global Foundries has
invested heavily in advanced
technologies including a
range of Silicon on
Insulator (SOI) processes
for advanced SoCs. This
process is ideal for devices
that must combine high
performance with extremely
low power consumption but
without the high cost of
FinFET manufacturing.
IP
vendors and SoC
manufacturers have shown a
great deal of interest in
this new process but are
faced with the perennial
problem of moving their
circuits from other
processes in order to obtain
the benefits it brings.
This is particularly
true where analog circuits
are involved as this usually
involves a full redesign
which is expensive in both
time and resources.
Migrating circuits to an SOI
process presents extra
challenges that were not
found in bulk silicon
technology.
Some devices may be
altered to take advantage of
the benefits of body biasing
so this must be addressed in
both the schematic and
layout.
Other factors like layer
coloring, dummy shapes and
layout dependent effects as
well as complex changes in
device construction and
rules must also be
considered.
IP
vendors always have to
confront the problems of
making their products
available in a variety of
foundries, processes and
options.
In an ideal world with
infinite time and resources,
designers would approach
each new technology with a
blank sheet of paper and
tailor their circuits to
suit.
However, engineering limits
and tight market windows
mean companies often don’t
have the luxury of extended
design cycles. If
circuits cannot be brought
to market quickly, IP
vendors will lose out on
lucrative licensing
opportunities while SoC
companies may have to make
compromises based on a
limited choice of available
products.
Synthesised digital circuit
design flows are regularly
used to move IP to new
processes but analog designs
are often reworked from the
ground up which takes long
time and pulls engineers
away from designing new
products.
An
alternative to full redesign
comes in the form of analog
and mixed signal circuit
migration.
This involves
translating existing
circuits to use elements
from a new process design
kit (PDK) and adapt to the
new rules and requirements
of the target foundry.
The structure,
hierarchy and architecture
remain the same as the
original so most of the
source data is reused
directly with adjustments to
suit the new technology.
Schematic circuits
can be made available for
simulation in a very short
time so decisions made about
functionality and circuit
enhancements.
Once the circuit is
validated in this way the
full migration can be
performed to deliver a
completed layout that meets
the needs of the target
foundry.
Migration can involve a port
of the entire circuit to the
new process to ensure IP is
available in the shortest
possible timeframe.
These designs will be
an exact replica of the
original with modifications
made to comply with the
requirements of the new PDK
and design rules.
Components and
interconnect will be
adjusted as required but
changes to the core circuit
will be kept to a minimum.
Engineers also have the
option to migrate the
schematics and optimise the
design using manual changes
or through a component
resizing tool such as
Cadence’s ADE GXL™
product.
This also allows designers
to take advantage of the
body biasing options
available in 22FDX® to
improve performance or
reduce leakage.
These changes can be
fed in to the physical
design where layout
engineers can update the
existing circuit or run
re-layout using guided
tools.
Global Foundries supports
the advance Virtuoso™
12.x environment where
layout dependent effect
awareness can be
incorporated in to the flow
to help guide the process.
Schematics and Simulation
The
first step in the migration
flow is usually to translate
the schematic and test bench
information in order to run
first level simulations.
Map files that
describe the old and new
circuit elements as well as
data on how to translate
parameters are called by the
migration tools to translate
the circuit hierarchy to the
new libraries and PDK.
Core circuit
components will be replaced
with equivalent devices from
the new PDK and any standard
cells placed in the analog
hierarchy should also be
swapped to elements from a
library in the new process.
Physical information such as
symbols, wires and pins are
migrated and adapted to suit
the elements in the new PDK
with automatic position
adjustment, rewiring, short
location and connectivity
checking tools.
Some SOI transistors
have extra pins for body
biasing so these must be
connected as required.
Automatic short
location within the
migration tools picks up any
places where a new pin
shorts to an existing wire
and re-routes to fix the
problem.
Migrating parameters is
often far more complex than
it first appears so the flow
must deal with differences
in parameter definition and
construction.
Translating IP from
the same foundry is usually
easier as most of a
foundry’s PDKs have a
similar construction but
converting data from
elsewhere is often much more
complex.
Differences in basic device
definition means that there
is no direct map from source
to target but even the most
complex conditional based
parameter mapping can be
built in to the flow.
All of this is
defined and controlled
within the migration tools,
making the details of the
conversion factors
transparent to the user.
Device size limits can also
play an important part in
process migration.
Tools must recognise
instances that can no longer
be drawn in the target
process due to limits in
maximum or minimum values
and adapt them accordingly.
For example, the
maximum finger width in
22FDX® may be smaller than
that allowed in an older
technology so devices must
be reconfigured to retain
their total size.
Old parameters that
are out of the reach of the
new PDK are a common issue
in design migration and the
OSIRIS flow will recognise
and reconfigure components
as required.
Similar changes are often
required in passive
components when size limits
many mean changes in the
number of segments in a
resistor chain or revised
multiples for a bank of
capacitors.
The migration flow
uses special call back
triggers in the target PDK
to set component values to
ensure that they are
properly calibrated.
There is no need for
the user to calculate
capacitance or resistance
per square in the old and
new processes and create
conversion factors for every
component themselves.
Once
the schematic migration is
complete and the test
benches are converted, the
circuit can run through
first level simulation.
This should confirm
overall functionality of the
system in the new process as
the simulation is using
models from the 22FDX®
libraries.
More accurate
simulation can be achieved
by using the ‘pre’ models
provided in the PDK to
include first level
estimates of parasitics in
the new process. Full Monte
Carlo analysis will give
more detailed data but first
order simulation will give
an overview of what can be
expected in the SOI process.
Designers may also wish to
boost circuit performance by
updating certain parts of
the circuit to take full
advantage of the features
available in SOI.
Body biasing could be
applied to input stages to
deliver faster switching and
large driving devices could
be given reverse body bias
to reduce leakage.
A migrated schematic
means that designers can get
to the circuit tuning level
without having to worry
about building an entirely
new design from scratch.
Once this migration
flow is configured, even
large designs can be
migrated and ready for
simulation in a matter of
hours.
Layout Migration
With
the schematic migrated and
first simulations run,
attention can turn to the
layout.
In cases where circuits that
have received extensive
changes, the layout may need
to be recreated and the
migrated schematic can
include pre-defined
constraints to drive a
guided layout flow.
An important feature
of any migrated database
must be that it can be used
and edited like any other
design so updates can be
made the migrated circuit at
will, just as if it had been
drawn directly in the 22FDX®
process.
If
the design has not been
extensively modified, the
OSIRIS layout migration
tools can translate the
design to the new process to
be verified against the
migrated schematic.
Layout migration is
much more complex than
translating schematics and
moving from bulk silicon to
an SOI process presents some
extra challenges.
However, a
comprehensive migration flow
will address the intricacies
of the different circuit
elements while giving
designers control and
flexibility to update the
circuits where necessary.
While schematic
migration is fully
automated, some sort of
interaction is usually
necessary during layout
migration to adapt the
design where necessary.
The
key to migrating analog
layout is to use foundry
elements in the target PDK
to build the migrated
design.
Parameterised cells
(Pcells), vias and shape
based data from the original
circuit are replaced by
elements from the new PDK
through the hierarchy with
component parameters adapted
as required.
A shape based flow
that reduces the design to a
collection of polygons will
never be able to convert
bulk silicon layout to SOI
but using Pcells means that
devices are correct by
construction wherever they
are placed.
The parameters for
active components are
adapted to match the
original while passives can
retain their value while
physical dimensions are
updated to give the correct
values in the new process.
Layout migration involves
much more than simply
plugging in new Pcells to
replace the old ones.
Differences in device
rules and construction
usually means that
components and routing don’t
line up any more and so the
tools have to apply extra
adjustments to the layout to
reconnect wires and
components.
Reconnection is
performed automatically in
the OSIRIS flow and retains
the matching and topology of
the original design; only
making small adjustments
where necessary.
Transistors are
pushed together to re-align
any source/drain overlaps
and the metal and vias moved
to their correct positions.
Extra reconfiguration
steps can also improve the
migrated layout including
automatic via staggering and
device or layer adjustment.
Metal coloring can
also be achieved in the flow
to satisfy the demands of
manufacturing in the new
process.
The
migration must be able to
deal with these differences
without any new database
requirements or the need to
have extra information added
to the source layout.
A migration flow that
needs to adjust the source
design in order to work
would be cumbersome and
would slow the process down
considerably.
The OSIRIS migration
reads the source layout as
is no matter where it came
from and the flow will deal
with differences between
source and target processes,
even if they are from
completely different
foundries.
The
complexity of parameters for
components in advanced
processes gives flexibility
but also places burdens on
tools and engineers.
The migration tools
cannot just set simple
dimension information and
leave everything else at
default values as this would
leave thousands of DRC
errors even in small
circuits.
IN2FAB’s OSIRIS tools can be
programmed to detrermine
which switches should be set
and apply the correct values
where requirements change
for each instance.
For example, internal
source/drain connections may
not be needed in certain
places and extra shapes such
as dummy poly are only
needed at the ends of
transistor rows.
These switches can’t
just be left to a layout
engineer as this would make
the whole task would
impossibly tedious.
Even
a simple transistor
placement can cause endless
problems.
In this instance, metal in
the Pcell causes a short
between source and drain and
dummy poly has been placed
where it is not needed,
violating the next
transistor in the row.
Differences in design
rules also mean that the
transistors no longer
overlap and the metal is
badly placed, even though
the old and new transistors
have identical width and
length values.
Switch control and automatic
reconnection will set the
transistor values correctly
and then align and adjust
the components as necessary.
Further adjustments
can be made through
automated tools or simply by
editing the layout to
deliver a migrated circuit
in a fraction of the time
taken for redesign.
IN2FAB’s OSIRIS migration
tools are fully integrated
with the Virtuoso tool suite
from Cadence Design Systems.
Designs are migrated
directly between old and new
processes within the Cadence
database meaning that PDKs
are used in their native
form rather than being
adapted or translated
through an external tool.
Migrating directly in
the Virtuoso editor also
means that optional
adjustments can be made
manually as the migration
progresses, enhancing the
circuit and taking advantage
of the hierarchy to manage
the migration processes.
Variations in processes and
device models can mean that
designs need several
modifications during
migration but these are
often restricted to specific
areas of the circuit.
A hierarchical and
flexible flow means that
these areas can be addressed
using the migrated design as
a base while the rest of the
design is migrated in
parallel, saving time and
resources to bring the
product to market.
Containing the migration
within the standard
schematic and layout editing
tools means that
modifications and tuning can
be performed at any time
without trying to squeeze it
in to the migration flow.
Using migration to
move the design to the new
process and tuning it
afterwards is far more
efficient and allows
dedicated simulation and
optimisation tools to do the
rest.
Conclusion
Rapid migration of analog
and mixed signal products
has long been a goal in
semiconductor design.
While digital
circuits can be
re-synthesized from a
high-level description,
analog engineers spend
endless time re-designing
the same circuits over and
over again whenever a new
process is needed.
A guided and flexible
migration flow drastically
reduces the effort involved
and makes effective design
reuse achievable.
Analog circuitry can be
migrated and tuned as
required while the digital
section can be regenerated
as required.
A migrated schematic
means that circuits can be
validated quickly and at
very low overhead while the
layout migration flow
ensures that the topology
and hierarchy of the
original design is
maintained as adjustments
are made to suit the new
process.
SoC companies can also
benefit by being able to
select IP based on desired
functionality or previous
experience knowing the
circuit can be moved to the
new technology quickly.
IN2FAB’s design migration
technology has been used to
move hundreds of circuits
between foundries and
process nodes.
While nanometre
design and SOI bring extra
challenges, SoC designers
and IP vendors can be
confident that using
IN2FAB’s OSIRIS migration
will bring major benefits
when moving their products
to 22FDX® and beyond.
About IN2FAB
IN2FAB Technology is the
world’s leading analog and
mixed signal process
migration company delivering
migration software and
services to the
semiconductor industry.
