Porting Case Studies - Migration to
0.13/0.18µm
Reconfigurable
Custom Semiconductor IP: UK based Fabless/IP Vendor
Type of chip/IP
- Reconfigurable custom semiconductor IP
Business Goals
- Migrate existing IP designed in UMC 0.18µm to TSMC 0.13µm
for a customer application
- Provide a mechanism for rapidly porting IP in comparison
to the manual method used previously
- Achieve optimal design shrink due to the emphasis on die
area
Source Process
Target Process
Size of die/IP pre migration
Size of die/IP post migration
Project Cycle time
- 3 calendar weeks for porting of layout to target process
Results
- IP subsequently acquired by an IDM
10
Bit ADC IP Module: European IDM
Type
of chip/IP
Business Goals
- Achieve
early availability of qualified ADC which will be used widely across
the corporation in 0.13µm in various SoC development programs
- Avoid greater than 12 month cycle time and re-spin taken to
redevelop a similar ADC for 0.13µm
Source Process
Target Process
Size of die/IP pre migration
Size of die/IP post migration
- Same (no shrink to analog section but digital shrink was
0.75x linear)
Project Cycle time
- 6 calendar weeks for porting of schematics and layout
including analog and digital blocks to target process
Results
- Working first time silicon
- Migrated ADC used in SoC designs in volume production
- Same ADC has subsequently been migrated to 90nm, 65nm and
45nm process nodes
Porting Case Studies Migration to 0.18µm
Analog
Mixed Signal IP Cores: US IDM
Type of chip/IP
- 13 analog mixed signal modules
Business Goals
- Achieve
fast cycle time and early availability of analog IP (developed at
0.25µm) in TSMC 0.18µm process to support a range of application
specific customer developments
- Achieve optimal design shrink due large percentage of
analog die area on chips
- Support fab-lite strategy
- Use trusted external resources due to lack of internal
resources
- Secure design-in wins through fast cycle time enabled by
migration approach
Source Process
Target Process
Size of die/IP pre migration
Size of die/IP post migration
Project Cycle time
- 7 calendar weeks for porting of layout and schematics to
target process
Results
- IP has been designed into to various customer application
specific projects
S-ATA:
US IP Vendor
Type of chip/IP
Business Goals
- Migrate
existing IP designed in TSMC 0.13µm to TSMC 0.18µm for a customer
application with fast cycle time to meet customer design-in target
- Provide a mechanism for rapidly porting IP in comparison
to the manual method used previously
- Achieve minimal design size increase
Source Process
Target Process
Size of die/IP pre migration
Size of die/IP post migration
- Confidential although there was an increase in size
Project Cycle time
- 5 calendar weeks for porting of schematic and layout to
target process/PDK
Results
- Migrated design signed off and in
production
Analog
Mixed Signal IP Cores: European IDM
Type of chip/IP
- 3 analog mixed signal modules including DAC, ADC
Business Goals
- Achieve
fast cycle time and early availability of analog IP (developed at
0.35µm) in internal 0.18µm process to support consumer application chip
developments
- Achieve optimal design shrink
- Fast cycle time enabled by migration approach
- Minimize impact to internal resources
Source Process
Target Process
Size of die/IP pre migration
Size of die/IP post migration
Project Cycle time
- 6 calendar weeks for porting of layout and schematics to
target process
Results
- Full IP miration success
- Designed into to various consumer application devices
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