OSIRIS Methodology

Working within the Cadence design framework, the OSIRIS tools provide the user with flexibility to modify the design at any stage of the migration process and make structural changes to their layout while OSIRIS takes care of data processing and shape based violations. The benefit of this approach is that designs of any size can be handled and the original intent of the designer is carried forward into the ported design.

The OSIRIS user interface automatically finds layers, symbolic devices and parameterized cells and allows easy mapping between the old manufacturing process and the new. Design data is mapped automatically or by user selection ensuring an easy transfer of data from one process to the next.

The new layout matches the old in topology and hierarchy, preserving critical circuit balance and matching without a lengthy set-up process or the overhead of the user having to generate design constraints.

he initial task involves analyzing the circuit along with the source and target design rules in order to determine the optimum size for the device in the new manufacturing process. Once this is complete, this provides all the information necessary for the layout to be scaled to the new size and modified to meet the constraints of the new manufacturing process design rules. The new die size for the design in the new rules is precisely known up front.

Maintaining Analog Performance

OSIRIS can be used for any geometry size and can cope with widely differing foundry styles such as extra implants and wells. The system is fully hierarchical and preserves the integrity of the original design by matching the topology and intent of the original design layout into which has gone considerable design effort.

Critical signals and device matching are maintained throughout the process without the need for intervention from the designer. Extra layers may be added and redundant layers removed giving complete foundry independence. Full control over power net sizing and via stacks is user definable and maintainable. The OSIRIS system is fully hierarchical and preserves both the hierarchy and topology of the original circuit, ensuring critical matching and wire positions are retained and layout intent preserved.

 

VCO section from a wireless device retargeted between IDM processes involving a geometry node change and die shrink. Overall chip port took 7 weeks including RF.

In analog designs, especially important is the ability to maintain exact physical or topological relationships. In this way the work of the original designer to ensure correct balancing and matching is exactly maintained. The fundamental principle behind the success that OSIRIS can bring is to create design right by construction. Because of this the first time success rate is always high for the ported design.

Working within the Cadence Design Framework II™ environment means that full maintainability and user control over the design both during the port and subsequently is ensured. OSIRIS is the vehicle to get to analog design completion rapidly.