45nm Migration Case Studies

Analog Mixed Signal IP Modules

European IDM

65nm and 45nm ported DAC reference section

Type of chip/IP:

• 20 analog mixed signal IP modules including ADCs, DACs, PLLs, bandgaps

 

Business Goals:

• Achieve early availability of qualified analog mixed signal modules used widely across the corporation in 65nm process node to support various SoC development programs
• Avoid the need to redesign existing IP or tie up valuable analog design resources
• Avoid estimated 15-18 month cycle time to redevelop the same IP for 45nm

 

Source Process:

• Crolles/TSMC compatible 65nm

 

Target Process:

• TSMC CRN45 45nm

 

Size of die/IP pre migration:

• Various

 

Size of die/IP post migration:

• Same

 

Project Cycle time:

• 16 calendar weeks for porting of layout and schematics to target process/PDK

 

Results:

• Working first time silicon achieved for all modules with initial characterization meeting specification

 

HDMI IP Core
European IDM

65nm and 45nm ported SerDes

Type of chip/IP:

• HDMI IP module

 

Business Goals:

• Achieve fast availability of HDMI IP core (TSMC 65nm) in 45nm process node to support other SoC developments
• Avoid the need to redesign existing IP or tie up valuable analog/RF design resources
• Avoid estimated 12 month cycle time to redevelop the same IP for 45nm

 

Source Process:

• Crolles/TSMC CLN065 65nm

 

Target Process:

• TSMC CLN045LP 45nm

 

Size of die/IP pre migration:

• Confidential

 

Size of die/IP post migration:

• Confidential

 

Project Cycle time:

• 7 calendar weeks for porting of layout and schematics to target process/PDK

 

Results:

• Deliverables have been accepted by customer and third party is doing silicon validation
• Customer has confirmed satisfaction with the results delivered

 

MIPI IP Core
European IDM

65nm and 45nm ported Rx Buffer

Type of chip/IP:

• MIPI D-PHY module

 

Business Goals:

• Achieve fast availability of MIPI IP core (TSMC 65nm) in 45nm process node to support other SoC developments
• Avoid the need to redesign existing IP or tie up valuable analog/RF design resources
• Avoid estimated 12 month cycle time to redevelop the same IP for 45nm

 

Source Process:

• Crolles/TSMC CLN065 65nm

 

Target Process:

• TSMC CLN045LP 45nm

 

Project Cycle time:

• 6 calendar weeks for porting of layout and schematics to target process/PDK

 

Results:

• Deliverables have been accepted by customer and third party is doing silicon validation
• Customer has confirmed satisfaction with the results delivered

 

Mobile 3G Platform IP

European IDM

    

65nm and 45nm ported 3G DAC

Type of chip/IP:

• 12 Mobile 3G platform analog mixed signal IP modules

 

Business Goals:

• Achieve early availability of 3G mobile IP modules (TSMC 65nm) in 45nm process node to accelerate mobile integration platform development in 45nm process technology
• Achieve aggressive market window to secure design-in wins with strategic customers
• Free up valuable analog/RF design resources to work on new IP and platform integration challenges by avoiding redesign of existing and proven IP
• Avoid estimated 18-24 month cycle time to redevelop the same IP for 45nm

 

Source Process:

• TSMC CLN065LP 65nm

 

Target Process:

• TSMC CLN045LP 45nm

 

Size of die/IP pre migration:

• Confidential

 

Size of die/IP post migration:

• Confidential

 

Project Cycle time:

• 14 calendar weeks for porting of layout and schematics to target process/PDK

 

Results:

• Deliverables have been signed off by customer
• Customer has confirmed satisfaction with the results delivered