0.25 Micron Migration Case Studies
ZFx86 Chip – 486 based application chip
US Fabless Vendor
Type of chip/IP
- 486 core with north bridge and south bridge, I/O, ESD and bond pad structures
Business Goals
- Migrate entire ZFx86 chip from National Semiconductor foundry due to end of life to IBM foundry
- Working design at earliest possible date due to limited inventory to meet customer demand
- Achieve working first time silicon and minimum yield targets
Source Process
- NSC cmos8 0.25µm
Target Process
- IBM CMOS6RF 0.25µm
Project Cycle time
- 6 calendar weeks for migration with a further 5 months in chip validation, OS and application testing
Results
- Currently in production
- Loaded BIOS and ran OS first time
Cell Library, Multiple Cells
US IDM
Type of chip/IP
- 453 cells for internal foundry
Business Goals
- Achieve early availability of cell library (developed for internal foundry) in TSMC 0.25µm process to support a range of application specific customer developments
- Support fab-lite strategy
- Use trusted external resources due to lack of internal resources
- Secure design-in wins through fast cycle time enabled by migration approach
Source Process
- Internal 0.25µm
Target Process
- TSMC CL025G 0.25µm
Size of die/IP pre migration
- Various
Size of die/IP post migration
- Same
Project Cycle time
- 5 calendar weeks for porting of layout and schematics to target process
Results
- Used in current development projects
- In volume production with various chips
Application Specific Analog Mixed Signal IP Core
US IDM
Type of chip/IP
- Application specific analog mixed signal IP core
Business Goals
- Achieve fast cycle time to support customer market window
- Achieve optimal design shrink
- Enable fab-lite strategy through porting internal IP to TSMC foundry
- Minimize impact to internal resources
Source Process
- Internal 0.6µm
Target Process
- TSMC CL025G 0.25µm
Size of die/IP pre migration
- Various
Size of die/IP post migration
- 0.5x linear shrink
Project Cycle time
- 5 calendar weeks for porting of layout and schematics to target process
Results
- IP successfully ported and signed off by customer
Porting Case Studies
Migration to 0.35µm
Cordless Chip
Europe based design group of a US Fabless Vendor
Type of chip/IP
- 2.4GHz Cordless chip with bond wire inductors
Business Goals
- Achieve early availability of qualified analog mixed signal modules used widely across the corporation in 90nm process node to support various SoC development programs
Source Process
- CSM 0.6µm BiCMOS
Target Process
- Jazz Semiconductor SBC35QTX 0.35µm SiGe
Size of die/IP pre migration
- 2880µm x 2765µm; 2239µm x 1585µm (IF block)
Size of die/IP post migration
- 0.75x linear shrink (2160µm x 2073µm; 1679µm x 1300µm)
Project Cycle time
- 9 calendar weeks for porting of layout
Results
- Ported silicon worked first time
- Achieved volume production
- Migrated design used for subsequent derivative products
Commercial Wireless Chip
Europe based design group of a US IDM
Type of chip/IP
- 2.4GHz commercial wireless chip containing significant RF, analog and digital block
Business Goals
- Foundry end of life for process line necessitated that the chip had to be migrated to company’s internal foundry process
- Achieve migration of the design with minimal disruption to existing engineering resources which were bandwidth constrained
- Fast migration to enable qualification and customer switch over at earliest possible time
Source Process
- ST 0.5µm BiCMOS
Target Process
- Internal 0.35µm BiCMOS
Size of die/IP pre migration
- Confidential
Size of die/IP post migration
- Confidential
Project Cycle time
- 8 calendar weeks for porting of layout
Results
- Ported silicon worked first time
- Achieved volume production